As one of semiconductor device wafers, there is an SOI (Silicon On Insulator) wafer having a silicon layer (which may be referred to as an SOI layer hereinafter) formed on a buried oxide film which is an insulator film. This SOI wafer has characteristics such as a small parasitic capacitance or high radiation hardness ability since the SOI layer of a substrate surface layer portion which becomes a device fabrication region is electrically separated from the inside of the substrate by the buried insulator layer (a buried oxide film layer (a BOX layer)). Thus, effects such as a high-speed low-consumption-power operation or soft error prevention are expected, and this wafer is regarded as a viable high-performance semiconductor device substrate.
The SOI wafer having a configuration including a base wafer, a BOX layer, and an SOI layer is generally often manufactured by a bonding method. This bonding method is a method of forming a silicon oxide film on, e.g., a surface of at least one of two silicon single crystal wafers, then pressing the two wafers against each other through the formed oxide film, performing a bonding heat treatment to enhance bonding strength, thereafter reducing a thickness of the one wafer (a wafer that forms the SOI layer (which will be referred to as a bond wafer hereinafter)) by mirror polishing or a so-called ion implantation delamination method to manufacture the SOI wafer.
In case of manufacturing the SOI wafer by such a bonding method, for the purpose of keeping a bonding interface away from the SOI layer on which a device is fabricated, it is often the case that the oxide film is formed on the bond wafer side.
On the other hand, speed improvement and capacity enlargement have been recently advancing in various communication devices. With this, performance improvement in radio frequency devices (RF devices) has been also demanded. Further, silicon photonics (Si photonics) to fabricate not only an electronic integrated circuit but also an optical integrated circuit on a silicon substrate has been also demanded. Some of bonded SOI wafers coping with these use applications are required to have a thick BOX oxide film. When the bonded SOI wafer includes the thick BOX oxide film, in terms of an upper limit of ion implantation energy, a technique to grow the thick oxide film on a base wafer side and perform bonding is used in some cases. Furthermore, when the thick oxide film is grown on the base wafer, a bonded SOI wafer manufacturing process is performed in a state where the thick oxide film is also provided on a back surface side which is opposite to a bonding surface of the base wafer.
To manufacture the bonded SOI wafer by the ion implantation delamination method, a step of improving flatness of an SOI layer surface after delamination is required. As this flattening step, there are a flattening step which is performed by using CMP (Chemical Mechanical Polishing) and a flattening step based on high-temperature annealing in a hydrogen gas or inert gas atmosphere (which may be referred to as a flattening heat treatment hereinafter). Usually, one of these steps is performed to the bonded SOI wafer after delamination.
Roughness of the SOI layer surface after the flattening step using CMP is equal to that of a mirror-polished wafer, but radial film thickness uniformity of the SOI layer tends to degrade. On the other hand, the flattening step based on high-temperature annealing results in roughness slightly higher than that of the mirror-polished wafer, but the film thickness uniformity of the SOI layer is good. In large-diameter wafers each having a diameter of 300 mm or more in particular, degradation of the film thickness uniformity at the flattening step using CMP is considerable. As compared with this, the flattening based on the high-temperature annealing does not have such a tendency.
As an example of a heat treatment to flatten the SOI layer surface by the high-temperature annealing, there is annealing in an argon atmosphere containing an argon gas which is an inert gas (which may be referred to as an Ar annealing hereinafter) (Patent Literature 1).
Although FIG. 1(e) and a paragraph [0047] in Patent Literature 1 have a description that an SOI wafer having an oxide film on a back surface thereof is subjected to a heat treatment in an inert gas atmosphere as the flattening heat treatment, it is preferable to perform the heat treatment at 1200° C. or more in case of an argon gas atmosphere (see a paragraph [0048] in Patent Literature 1).